Programming an electronic device including a non-volatile memory, in particular for adjusting the features of an oscillator

ABSTRACT

There is described an electronic device including an electronic circuit ( 1, 8 ) for delivering an output signal (CKS) and a programmable non volatile memory ( 30 ) coupled to the electronic circuit to allow storage of a binary word (EED[7:0]) representative of at least one adjustable feature (C 1 , C 2 ) of the electronic circuit ( 1, 8 ), this electronic device including at least first and second supply terminals (PAD_VDD, PAD_VSS), to which first and second supply voltages are applied (V DD , V SS ) and at least one output terminal (PAD_OUT) at which the output signal from the electronic circuit is delivered,  
     Means are provided for switching the output terminal into a so-called high impedance state so as to allow the introduction, in serial form, via this output terminal, of data bits intended, in particular, to be stored in the non volatile memory of the device.  
     This device is applied, in particular, for adjusting the features of an oscillator circuit.

[0001] The present invention concerns generally the programming of anelectronic device including a memory. More particularly, the presentinvention concerns the programming of a memory for adjusting thefeatures of an oscillator.

[0002] It is now common to fit electronic devices with a non-volatilememory for the purpose of adjusting certain operating features of theelectronic device. It is for example already known to program a memoryof an electronic device including a time base and a frequency dividercircuit in order to store a binary word representative, for example, ofthe division rate of the frequency divider circuit.

[0003] By way of example, Swiss Patent document CH 664 868 discloses aprogramming device of a non-volatile memory for a timepiece by means ofwhich the division rate of the frequency divider circuit is adjusted byintroducing into the memory a number representative of the difference infrequency between the time base frequency and a standard frequency.According to this document, programming is advantageously carried outvia two supply terminals to which the timepiece battery is normallyconnected.

[0004] This solution has the advantage of not requiring any additionalterminals to program the non-volatile memory. The use of the supplyterminals of the device to program the memory has, however, a drawbackin the sense that the supply voltage of the electronic device and thevoltage levels necessary for programming typically have to be fixed atpredetermined levels. Moreover, the use of the supply terminals asprogramming terminals means that the electronic device has to bedesigned such that the components normally powered are not disturbedwhen data is introduced. Yet another drawback of this solution also liesin the fact that the powering of the electronic device typically has tobe interrupted to access the supply terminals.

[0005] One object of the present invention is to propose a solution forprogramming a non-volatile memory of an electronic device, which doesnot require the use of the device's supply terminals.

[0006] Another object of the present invention is to propose a solutionpreferably using existing terminals of the electronic device to carryout programming of the non-volatile memory.

[0007] More particularly, the object of the present invention is topropose such a solution allowing the features of an oscillator circuitto be adjusted.

[0008] The present invention thus concerns an electronic deviceincluding a programmable non-volatile memory whose features are listedin independent claim 1.

[0009] The present invention also concerns a method for programmingand/or reading a programmable non-volatile memory of an electronicdevice whose features are listed in independent claim 10.

[0010] Advantageous embodiments of the present invention form thesubject of the independent claims.

[0011] In particular, the present invention concerns more particular anelectronic device including an oscillator circuit having an adjustablefeature.

[0012] One advantage of the present invention lies in the fact that, inaddition to the two supply terminals of the device and an outputterminal through which an output signal of the device is delivered, itrequires only one control terminal, accessible from the exterior, i.e. aminimum of four external terminals. This constitutes a very significantadvantage, in particular during assembly and packaging of an electronicdevice of reduced size, such as an integrated electronic component, likean oscillator circuit, for example. In particular, the reduced number ofrequired terminals only involves limited bonding and connectingoperations between the terminals of the integrated circuit itself andthe connection terminals of the package in which the integrated circuitis packaged.

[0013] Within the scope of a specific application to an oscillatorcircuit, the present invention allows, in particular, a component ofvery compact size to be made, whose features it is possible to adjust.

[0014] Other features and advantages of the present invention willappear more clearly upon reading the following detailed description,made with reference to the annexed drawings, given by way of nonlimiting example, and in which:

[0015]FIG. 1 is a diagram of an inverter type oscillator circuit having,in particular, first and second load capacitors placed at the input andoutput of the inverter;

[0016]FIG. 2 is a schematic perspective view of the lower face of an SMDelectronic component, such as an oscillator circuit, including only fourconnection terminals, namely two supply terminals, a control terminaland an output terminal;

[0017]FIG. 3 is a block diagram of an electronic device including anoscillator circuit implementing the present invention;

[0018]FIG. 4 is a detailed diagram of an output stage of the device ofFIG. 3;

[0019]FIG. 5 is a detailed diagram of a circuit generating activationsignals STARTUP and TIMEOUT_n evolving over time;

[0020]FIG. 6 is a diagram illustrating the shape of the data bits andclocking signals generated by the device of FIG. 3;

[0021]FIG. 7 is a diagram of a switched capacitor network of the deviceof FIG. 3 allowing adjustment of the capacitance value of the loadcapacitors of the oscillator circuit of FIG. 1;

[0022]FIG. 8 is a detailed diagram of a switch used in the switchedcapacitor network of FIG. 7;

[0023]FIG. 9 is a detailed diagram of a serial communication interfaceof the device of FIG. 3;

[0024]FIG. 10 is a detailed diagram of a circuit detecting theapplication, at a control terminal of the device of FIG. 3, of adetermined voltage level;

[0025]FIG. 11 is a detailed diagram of a read and write operationcontrol unit for the interface of FIG. 9; and

[0026]FIG. 12 is a detailed diagram of an output interface of the serialcommunication interface of FIG. 9 allowing an output signal DATA_OUT tobe delivered, which signal is representative of the data stored in thememory of the device of FIG. 3.

[0027] In the following part of the present description, an embodimentexample of an oscillator circuit incorporating the solution according tothe present invention, will now be described. “Oscillator circuit” meansan electronic circuit delivering an alternating output signal oroscillating signal at at least one frequency and including at least oneresonant element and an electronic supply and maintenance circuit forthe vibrations of the resonant element. Various types of oscillatorcircuits are already known from the prior art. By way of information,one could for example refer to European Patent Application No. EP 1 111770 A1 (incorporated herein by reference) which discloses a lowfrequency quartz oscillator device having improved thermal behaviour.This oscillator device employs a quartz resonator able to vibrate atleast according to a fundamental torsional vibration mode and aninverter type vibration maintenance circuit arranged to maintain theresonator vibrations according to the torsional vibration mode.

[0028]FIG. 1 is a schematic diagram of the oscillator device of theaforementioned Application. This oscillator device, globally indicatedby the reference numeral 1, essentially includes the parallelarrangement, between input terminal A and output terminal B, of aso-called feedback resistive element 4, of resistance value R_(F), aninverter amplifier means 2, and a resonator 3, here a quartz resonator.First and second load capacitors 5 and 6, of capacitance value C₁ andC₂, are respectively connected between input terminal A and outputterminal B, on the one hand, and a circuit supply potential, on theother hand, such as a low potential V_(ss) forming ground (these loadcapacitors 5 and 6 may alternatively be connected to a high potentialV_(DD)). By way of option, an additional resistive element 7, ofresistance value R₀, can be connected in series between the output ofamplifier means 2 and resonator 3 as illustrated, in order to improvethe oscillator circuit's stability.

[0029] The oscillator device of FIG. 1 may advantageously beincorporated with its resonator in a single package of reduced size (forexample a ceramic package of the order of several mm²). FIG. 2 shows aschematic perspective view of the lower face of an SMD (Surface MountedDevice) type electronic device including such a package 10 intended toincorporate the oscillator device of FIG. 1. The device mounted in itsSMD package only includes, in this example, four connection terminals 1a, 1 b, 1 c and 1 d, namely two supply terminals 1 d and 1 b(respectively designated PAD_VDD and PAD_VSS in the followingdescription), a control terminal 1 a (designated PAD_OE) and an outputterminal 1 c (designated PAD_OUT).

[0030] As already mentioned in the preamble of the present description,it is desirable to be able to adjust certain features of the electronicdevice, in particular at the end of the assembly and packaging of theelectronic component. In this case, it is for example desirable to beable to adjust the capacitance values of load capacitors 5 and 6 of theoscillator device of FIG. 1. The following description will show howsuch adjustment is made possible despite the very reduced number ofconnection terminals.

[0031]FIG. 3 is a block diagram of an embodiment of the presentinvention allowing adjustment of capacitance values of load capacitors 5and 6 of the oscillator device of FIG. 1. Quartz oscillator 3 can beseen again connected via its terminals A, B to inverter oscillatorcircuit 1. The value of load capacitors 5, 6 can be digitally adjustedby a binary word (in this example an 8-bit binary word EED [7:0]) ableto be stored in a non-volatile memory 30, for example of the EEPROM(Electrically Erasable and Programmable Read Only Memory) type.

[0032] By way of illustration, oscillator circuit 1 is arranged todeliver an alternating output signal having a frequency substantiallyequal to 393,216 kHz (cf. the aforementioned European PatentApplication), this signal being applied to the input of a dividercircuit 8 allowing the frequency of the input signal to be divided to atleast a first frequency substantially equal, in this example, to 32,768kHz (=393,216 kHz/12). This divider circuit also delivers various otherclock signals to the various elements of the electronic device, namelyin particular, signals of respectively 128 Hz, 512 Hz and 2 kHz. Thenumerical values of these frequencies (and the other numerical valuesmentioned in the present description) are of course given solely by wayof example and are in no way limiting of the scope of the invention.

[0033] The signals delivered at the output of oscillator circuit 1(signal at 393,216 kHz) and at the output of divider circuit 8 (signalat 32,768 kHz) are applied to a first selection stage 15. This selectionstage 15 includes a control terminal, designated S, not accessible fromthe exterior of the package, allowing selection during manufacture (forexample via making or not making of a metallisation) which of thesignals at 393,216 kHz (S a the high logic state) or 32,768 kHz (S atthe low logic state) has to be delivered at the output of selectionstage 15 (signal CKS).

[0034] A second selection stage 16 is arranged downstream of selectionstage 15 for delivering an output signal designated CK_OUT which isequivalent, as a function of the control signal applied to this stage,either to signal CKS emanating from first selection stage 15 or to readdata DATA_OUT representative of the binary word stored in EEPROM memory30 and to which we will return in more detail in the following part ofthe description.

[0035] The output signal CK_OUT is applied through an AND gate to afirst input (signal OUT) of an output stage 20 connected to outputterminal PAD_OUT. Output stage 20 includes a second input to which isapplied a control signal, designated HZOUT, allowing the impedance stateof output PAD_OUT to be controlled, as will be seen hereinafter. FIG. 4illustrates a detailed example of output stage 20.

[0036] The device illustrated in FIG. 3 further includes a serialcommunication interface 40 connected in particular to output and controlterminals PAD_OUT and PAD_OE. As will be seen hereinafter in detail,communication interface 40 assures, in particular, control of theimpedance state of output stage 20, control of the state of secondselection stage 16 and the programming and reading of non-volatilememory 30. For the programming and read operations of non-volatilememory 30, interface 40 co-operates with a control circuit 35 of theEEPROM memory. The practical making of control circuit 35 or EEPROMmemory 30 will not be described here in detail, since these elements arewell known to those skilled in the art. One will simply mention thatEEPROM memory 30 has sufficient capacity to store binary word EED[7:0](namely at least 8 bits in this example), that communication interface40 is arranged to deliver, for memory 30 and control circuit 35, a writeactivation signal (designated EEPROG_ST) to start writing the binaryword in the memory and that control circuit 35 is arranged to deliver anactivation signal, designated EEPROG_EN, when the memory is activated.It will also be noted that activation signal EEPROG_ST (namely a clockpulse) is generated when the write mode is interrupted in order to startthe write phase in EEPROM memory 30 of data loaded by interface 40.

[0037] The data bits having to be stored in EEPROM memory 30 aredesignated D[i], i=0 to 7, and are transmitted by interface 40 to memory30 by a first data bus 42 (of 8 bits in this example). Likewise, thedata bits stored in the memory, designated EED[i], i=0 to 7, aretransmitted on a second data bus 48 (also of 8 bits in this example) toadjustable capacitors 5 and 6, on the one hand, and to interface 40, onthe other hand, for the purpose of reading.

[0038] The device illustrated in FIG. 3 also includes a power on resetor POR cell 60, a bias circuit 70 and an activation signal generatorcircuit 80. The power on reset cell 60, which can be any type of cellwell known to those skilled in the art, has the essential function ofdelivering a zero reset signal RESET in a conventional manner when theelectronic circuit is started, provided that the supply voltage remainslower than a determined initialisation threshold. This reset signalRESET is applied, in particular, to frequency divider circuit 8, tointerface 40, to generator circuit 80, to EEPROM memory 30 and tocontrol circuit 35.

[0039] Bias circuit 70 assures biasing and a regulated supply, inparticular, of power on reset cell 60 (in this example via a biascurrent designated IB_POR), of oscillator circuit 1 (via a bias currentIB_OSC and first and second regulated supply voltages VBP and VR), ofdivider circuit 8, and of control circuit 35 of memory 30 (via areference current IREF_READ). Unless otherwise indicated, the variouselements of the circuit are powered by the voltage present across supplyterminals PAD_VDD and PAD_VSS of the circuit. Certain elements, such asoscillator 1 or divider circuit 8, are however powered at leastpartially, by a regulated intermediate supply potential VR delivered bybias circuit 70.

[0040] Activation signal generator circuit 80 is arranged to deliver afirst activation signal, designated STARTUP, for controlling the stateof oscillator circuit 1 during its start up phase, and a secondactivation signal, designated TlMEOUT_n, or more exactly an expirysignal, used in particular during read and programming operations ofEEPROM memory 30. In particular, the signal TIMEOUT_n defines adetermined time interval during which the read or write operations canbe undertaken. At the end of this determined time interval, the devicereturns to its normal mode where it delivers the frequency signal CKS atone output. One need only to know at the moment that the first andsecond activation signals STARTUP and TIMEOUT_n each pass to a low logicstate at the end of a determined time interval, respectively of 125 msand 250 ms in this example. A detailed example of generator circuit 80is illustrated in FIG. 5.

[0041] With reference again to transmission interface 40, it will benoted that it delivers a certain number of control signals which willnow be briefly described. This various control signals are designatedENREAD_n (Not Enable Read), PROG_EN_n (Not Program Enable) and PROG_ENHZ(Program Enable High Impedance). By convention, the signal expressionsfollowed by the index “_n” indicate that the signal is the opposite orinverse of the signal having the same prefix, i.e. ENREAD_n andPROG_EN_n are for example respectively the inverse of the signals ENREADand PROG_EN.

[0042] Generally, the signal PROG_EN_n indicates whether the system isin a communication mode (PROG_EN_n at “0”) where interface 40 is activeand where data can be introduced into (write mode) or extracted from(read mode) EEPROM memory 30. According to the invention, the device isswitched into communication mode by applying a determined voltage tocontrol terminal PAD_OE. In the example which will be describedhereinafter, this switching is for example carried out by applying avoltage equal to half the supply voltage to terminal PAD_OE, i.e.V_(DD)/2 (assuming V_(ss)=0).

[0043] The signal ENREAD_n indicates, in the case in which the devicehas been previously switched into communication mode, whether the systemis specifically in the so-called read mode (ENREAD_n at “0”) where onewishes to read the data stored in EEPROM memory 30. The signal PROG_ENHZcontrols the impedance state of output stage 20 in write mode.

[0044] As illustrated in FIG. 3, the signals ENREAD_n and PROG_EN_n, onthe one hand, and PROG_ENHZ, on the other hand, are used to control theimpedance state of output stage 20. In this case, the signals ENREAD_n,PROG_EN_n and the inverse OE_n of signal OE applied to control terminalPAD_OE and the inverse TIMEOUT_n of activation signal TIMEOUT deliveredby generator circuit 80, are applied to an AND gate with four inputs,the output of which is applied to the second control terminal (HZOUT) ofoutput stage 20 through an OR gate with three inputs followed by an ANDgate with two inputs. Signal PROG_ENHZ and activation signal EEPROG_ENof memory 30 originating from control circuit 35 are applied to thesecond control terminal of the output stage through the two remaininginputs of the OR gate.

[0045] It will be noted that the signal originating from the OR gate,designated EN_HZOUT, and signal CK_OUT originating from second selectionstage 16 are respectively applied to the first OUT and second HZOUTinputs of stage 20 each through an AND gate with two inputs, the signalSTARTUP_n being applied to the second input of each of these two ANDgates. During the start-up phase of the oscillation circuit, the signalSTARTUP is at the high logic state, thus blocking the two AND gates atthe input of output stage 20. As soon as the oscillator circuit is in asteady state, at the end of a determined interval of time, fixed in thisexample to 125 ms, the signal STARTUP passes to the low logic state thusfreeing the two AND gates.

[0046] With reference to FIG. 4, the structure and operation of outputstage 20 will now be described in more detail. As illustrated, stage 20includes, in particular, the series arrangement, between supplypotentials V_(DD) and V_(SS), of a p-MOS transistor 21 and an n-MOStransistor 22. The connection node of transistors 21 and 22 is connectedto the output terminal PAD_OUT of the device.

[0047] The gate of p-MOS transistor 21 is controlled by the signaloriginating from a NAND gate with two inputs to which are applied thefirst input signal OUT and the inverse of the second input signal HZOUT.The gate of n-MOS transistor 22 is controlled by the signal originatingfrom a NOR gate with two inputs to which are applied signal OUT andsignal HZOUT. The table below summarises the state of output PAD_OUT asa function of input signals OUT and HZOUT: HZOUT OUT PAD_OUT Comments 00 V_(ss) output to ground (RESET) 0 CKS, CKS, frequency or data signalDATA_OUT DATA_OUT delivered at output 1 0, 1 HIGH- output capable ofIMPEDANCE receiving data

[0048] With reference to FIGS. 3, 4 and to the table above, it will beunderstood that signal HZOUT is brought to the high logic state(assuming that signal STARTUP_n is in the high logic state) (1) ifactivation signal EEPROG_EN is at the high logic state, (2) if controlsignal PROG_ENHZ is at the high logic state, or (3) if the signalresulting from the AND logic combination of signals OE_n, TIMEOUT_n,ENREAD_n and PROG_EN_n is at the high logic state. In other words,output PAD_OUT is in the high impedance state (1) if memory 30 isactive, (2) if the system is in write mode, or (3) if control terminalPAD_OE is brought to ground V_(SS) while the system is neither incommunication mode (PROG_EN=0), nor in read mode (EN_READ=0) and expirysignal TIMEOUT is at the low logic state (TIMEOUT_n=1).

[0049] In this high impedance state, output PAD_OUT can thus be used asan input terminal, in particular for introducing in serial form datawhich has to be stored in EEPROM memory 30 as will be seen hereinafter(FIG. 6 shows the shape of data bits transmitted to or by serialcommunication interface 40). As illustrated in FIG. 3, serialcommunication interface 40 thus includes a data input DATA_IN directlyconnected to output terminal PAD_OUT.

[0050] As soon as signal HZOUT is at the low logic state, output PAD_OUTtakes the state of the first input of stage 20 to which is applied thesignal OUT, i.e. frequency signal CKS or data signal DATA_OUT deliveredby a data output of interface 40 as a function of the state of selectionstage 16. During the start-up phase (STARTUP_n=0), output PAD_OUT isforced to ground V_(SS).

[0051] By means of FIG. 5, an embodiment example of circuit 80 forgenerating activation signals STARTUP and TIMEOUT will now be brieflydescribed. As already mentioned hereinbefore, signal STARTUP takes thehigh logic state during start-up of oscillator circuit 1 and passes tothe low logic state at the end of a determined interval of time, fixedby way of example to 125 ms, directly following initialisation of thedevice. The inverse TIMEOUT_n of signal TIMEOUT is at the high logicstate as long as the device is not switched into communication mode(PROG_EN=0) and passes to the low logic state at the end of a determinedtime interval, fixed by way of example to 250 ms, following the passageto the high logic state of signal PROG_EN.

[0052] In FIG. 5, the signal designated RESTIM_n corresponds to thecontrol signal PROG_EN (cf. FIG. 9) and the signal designated EOTRANSMITis a signal indicating the end of the data loading process, in writemode, or the end of the data transmission process, in read mode (cf.FIGS. 9 and 11). These signals RESTIM_N and EOTRANSMIT are transmittedto generator circuit 80 by interface 40. Clock signal CK_(—)128 is aclock signal delivered by frequency divider circuit 8 having, in thisexample, a frequency of 128 Hz.

[0053] Generator circuit 80 of FIG. 5 includes a counter 81 (in thiscase a counter-by-32) delivering at one output a first signal intendedto reset terminal R of a first bistable trigger circuit S-R 85 and asecond signal intended for excitation terminal S of a second bistabletrigger circuit S-R 83. The first output signal of counter 81 takes thehigh logic state as soon as 16 pulses have been counted (16×{fraction(1/128)}=125 ms). The second output signal takes the high logic state assoon as 32 pulses have been counted by counter 81 (32×{fraction(1/128)}=250 ms).

[0054] Excitation terminal S of first bistable trigger circuit S-R 85 iscontrolled by the inverse RESET_n of initialisation signal RESET. Theinverted output of this first bistable trigger circuit 85 delivers theinverse STARTUP_n of the signal STARTUP, the latter being applied to afirst input of an OR gate with two inputs. The signal RESTIM_n(=PROG_EN) is applied to the second input of this OR gate. The output ofthe OR gate and the signal RESET_n are applied to the two inputs of aNAND gate whose output controls initialisation terminal R of counter 81as well as the clock input of this counter 81 via a NOR gate.Initialisation signal RESET as well as the end-of-transmission signalEOTRANSMIT are both applied to initialisation terminal R of secondbistable trigger circuit S-R 83, at the inverted output of which isdelivered signal TIMEOUT_n.

[0055] Those skilled in the art will easily understand, upon readingFIG. 5, that the counter is activated for the first time as soon asinitialisation signal RESET passes to the low logic state, signalSTARTUP then taking the high logic state for 125 ms to return to the lowlogic state at the end of this time interval, counter 81 then beinginitialised again (RESTIMEOUT=1). As soon as the device's communicationmode is activated following detection of the application of voltageV_(DD)/2 to control terminal PAD_OE, signal RESTIM_n (=PROG_EN) takesthe high logic state and starts counter 81. Signal TlMEOUT_n keeps thusits high logic state during 250 ms to pass to the low logic state at theend of this time interval. It will be noted that signal TIMEOUT_n keepsthe high logic state at the end of the 250 ms if the end-of-transmissionsignal EOTRANSMIT passes to the high logic state during this sameinterval.

[0056] In the embodiment example illustrated in the Figures, datatransmission to or from serial communication interface 40 employs apulse width modulation technique. A non-limiting example is illustratedin FIG. 6.

[0057] According to this example, a data bit has a period ofapproximately 7.812 ms equivalent to sixteen successive pulses of aclock signal of 2 kHz (also delivered by the frequency divider circuit,signal CK). More specifically, a data bit “1” is defined as a signalwhich is at the high logic level for approximately 5.859 ms (i.e. twelvesuccessive pulses of the clock signal) then at the low logic level forthe rest of the period (i.e. the remaining four clock pulses).Conversely, a data bit “0” is defined as a signal which is at the highlogic level for approximately 1, 953 ms (i.e. four successive pulses ofthe clock signal) then at the low logic level for the rest of the period(i.e. the remaining twelve clock pulses). According to the embodimentexample of the present invention, the data bits are introduced (DATA_IN)or extracted (DATA_OUT) in accordance with the diagram of FIG. 6.

[0058] With reference now to FIG. 3 and to FIGS. 7 and 8, the structureof the adjustable load capacitors 5 and 6, whose value is controlled bythe state of the binary word stored in EEPROM memory 30, will now bebriefly described. In the example of the Figures, the value of loadcapacitors 5, 6 is adjusted as a function of an 8-bits binary word ofEED[7:0] stored in memory 30. The two most-significant bits EED[7] andEED[6] define the capacitance value of load capacitor 6 placed at theoscillator output terminal B (OSCOUT) and the six other bits EED[5] andEED[0] define the capacitance value of capacitor 5 placed at theoscillator input terminal A (OSCIN).

[0059] In accordance with the illustration of FIG. 7, each capacitor isformed of the parallel arrangement of a nominal capacitor COUT_(—)0,respectively CIN_(—)0, and several capacitors each connected in serieswith a switch TO2, TO1, respectively TI32, TI16, TI8, TI4, TI2 and TI1,controlled by the state of the corresponding bit of the stored wordEED[7:0].

[0060] Analytically, the capacitance value of input capacitor 5 andoutput capacitor 6 is defined as follows:${C_{IN} = {{{CIN\_}0} + {\sum\limits_{i = 0}^{5}{{2^{i} \cdot {{EED}\lbrack i\rbrack} \cdot \Delta}\quad C_{STEP}}}}}\quad$$C_{OUT} = {{{COUT\_}0} + {\sum\limits_{i = 6}^{7}{{2^{i - 1} \cdot {{EED}\lbrack i\rbrack} \cdot \Delta}\quad C_{STEP}}}}$

[0061] Where ΔCSTEP is equivalent in this case to 0.1 pF and whereCIN_(—)0 and COUT_(—)0 have been chosen respectively, purely by way ofillustration, at 1 pF and 10 pF. The capacitance value is thusweightened as a function of the weight of the bit concerned. Thecapacitance value of input capacitor 5 is thus adjustable from 1 pF to7.3 pF by steps of 0.1 pF, and the capacitance value of output capacitor6 from 10 pF to 19.6 pF by steps of 3.2 pF. The fact that theaforementioned numerical values are only illustrative and in no wayconstitute a limitation of the scope of the invention should be stressedagain.

[0062] Preferably, switches TO1, TO2, and TI1 to TI32 are configured tooperate at reduced voltages. FIG. 8 shows an embodiment example of sucha switch, or transmission gate, including, in particular, the parallelarrangement of an n-MOS transistor 55 and a p-MOS transistor 65connected to each other via their drain and source terminals. In thisexample, in order to reduce the operating voltage of the device, oneacts on the threshold voltage of at least one of the two transistors 55,65, via is bulk terminal. In this case, the threshold voltage of n-MOStransistor 55 is acted on by means of an additional p-MOS transistor 56whose source is connected to the bulk terminal of n-MOS transistor 55and whose drain is connected to the source of n-MOS transistor 55. Thegate of n-MOS transistor 55 is controlled by the state of thecorresponding memory bit [i] and the gates of p-MOS transistors 65 and56 by the inverse state EED[i] _n of the memory bit.

[0063] It will be noted that it is alternatively possible to act on thethreshold voltage of p-MOS transistor 65 via an additional n-MOStransistor or even to act simultaneously on the threshold voltages ofn-MOS transistor 55 and p-MOS transistor 65, these possibilities beingessentially determined by the technology used and the availability of anindividual contact with the bulk terminal of each transistor. By way ofexample, BICMOS or SOI (Silicon on Insulator) technology makes suchindividual contact with the transistor bulk possible.

[0064] With reference to FIG. 9, the general operation of serialcommunication interface 40 will now be described. The latter essentiallyincludes a communication mode detection and activation unit 41 connectedto control terminal PAD_OE, a shift register 43 for allowing serialloading of data introduced via output terminal PAD_OUT at data inputDATA_IN of the interface, a key decoding circuit 45, a read and writeoperation control unit 47, and an output interface 49 for the serialemission, during a read operation, of stored data bits.

[0065] The table below summarises the states of the main signals as afunction of the operating state of the interface: State PROG_ENPROG_ENHZ ENREAD_n TIMEOUT_n Initialisation 0 0 1 1 RESET = 1 Normalmode 0 0 1 1 RESET = 0 STARTUP = 1 Communication 1 1 1 1 (t < 250 ms)and write mode (no read) Read mode 1 0 0 1 (t < 250 ms) Expiry of time 00 1 0 then return to (t > 250 ms) 1 after initialisation

[0066] Generally, a write or read operation of EEPROM memory 30 startswith the activation of the interface communication mode. This activationis carried out, as already mentioned, by applying a determined voltage,in this example half V_(DD)/2 of the supply voltage, to control terminalPAD_OE. FIG. 10, which will be discussed in more detail hereinafter,presents an embodiment example of detection circuit 41 deliveringactivation signal PROG_EN (as well as auxiliary activation signalsdesignated QOE2 and QOE1_n). As will be understood upon reading FIG. 10,auxiliary signal QOE2 is configured to pass back to the low logic levelwith a certain delay with respect to signal PROG_EN. This signal QOE2 isused, in particular, to keep output PAD_OUT for a short moment in thehigh impedance state when the application of the switching voltage atcontrol terminal PAD_OE is stopped. Likewise, signal QOE1_n and signalQOE2 are used jointly (in combination with expiry signal TIMEOUT_n,clock signal CK and two additional auxiliary signals) for generating aclock pulse EEPROG_ST for a memory write operation.

[0067] As illustrated in FIG. 9, control signal PROG_ENHZ is derivedfrom the AND logic combination of signal ENREAD_n, TIMEOUT_n and thesignal resulting from the OR logic combination of signals PROG_EN andQOE2. Thus, as soon as the signal PROG_EN passes to the high logic state(or the signal QOE2 is still in this state), the control signalPROG_ENHZ is activated to switch output stage 20 of the device into thehigh impedance state and allow introduction of data via output terminalPAD_OUT.

[0068] The introduced data DATA_IN is delivered to the input of an ANDgate which is additionally controlled by signal PROG_EN and a controlsignal TEN (“Transmission Enable”). This control signal TEN is normallyat the high logic state and only passes to the low logic state if theinterface read mode is activated as will be understood upon reading FIG.11 hereinafter. In the normal state, thus, the AND gate is conductingand delivers the introduced data, designated DATA, to the output of theAND gate, at the input of shift register 43.

[0069] This shift register 43 includes in this example nine positions inorder, in particular, to allow loading of eight data bits as well as aninth so-called parity bit allowing any transmission error check. Inthis regard, a parity check unit 44 is connected to the nine positionsof shift register 43, this check unit delivering an activation signalENPARITY passing to the high logic state if the parity of the sequenceintroduced is correct.

[0070] The shift register is clocked by a clock signal SCK generated bycontrol unit 47. This clock signal SCK illustrated in FIG. 6, in thesame way as clock signals S4CK_n, S12CK_n and S16CK, essentiallyconsists of a pulse at the high logic level coinciding with the eighthpulse of reference signal CK. At each pulse of signal SCK, thecorresponding value of the input signal, i.e. the high logic levelduring transmission of bit “1” or the low logic level duringtransmission of bit “0” as illustrated in FIG. 6, is loaded in aposition of shift register 43.

[0071] Preferably, and for reasons of security, the introduction of datastarts with the transmission of a write or read key preceding the actualdata bits. In this example, the data takes the form of a sequence ofthirteen bits:K[3]-K[2]-K[1]-K[0]-D[7]-D[6]-D[5]-D[4]-D[3]-D[2]-D[1]-D[0]-Ptransmitted in accordance with the diagram of FIG. 6 and including fourfirst key bits K[3] to K[0], eight data bits D[7] to D[0] (transmittedfrom the most-significant bit to the least-significant bit) and a paritybit P.

[0072] Thus, the four key bits K[3], K[2], K[1] and K[0] are first ofall loaded respectively in positions D[2], D[1], D[0] and P of shiftregister 43. These first four positions are connected to the inputs ofkey decoding circuit 45 which generates at one output a first signaldesignated READ_n taking the low logic state if the read key (READ KEY)has been introduced, and a second signal designated CLOSELOCK_n takingthe low logic state if the write key (WRITE KEY) has been introduced.

[0073] Generally, if none of the keys provided is introduced, dataloading into shift register 43 is interrupted by the passage of signalTEN applied to AND input gate to the low logic state. Likewise, if theread key has been introduced, signal TEN also passes to the low logicstate in order to lock the input of shift register 43. Conversely, inthe event that the write key has been introduced, signal TEN remains atthe high logic level in order to allow data loading to continue, i.e.loading of data bits D[7] to D[0] and parity bit P.

[0074] The read and write processes will be explained in more detailhereinafter with reference to FIG. 11. It will be noted already thatread and write operation control unit 47 receives at one input clocksignal CK (here at 2 kHz), signal DATA originating from the AND inputgate (this signal being used as a synchronisation signal in particularfor deriving clock signal SCK from shift register 43), a clock signalCKDATA_OUT, in this example of 512 Hz (used in particular for derivingclock signals SCK, S4CK_n, S12CK_n and S16CK during the read process),initialisation signal RESET and read and write key introductionindicators READ_n, CLOSELOCK_n. Control unit 47 delivers at one outputclocking signals SCK, S4CK_n, S12CK_n and S16CK, selection signals S0,S1, S2 for output interface 49, read mode activation signal ENREAD_n, awrite mode activation signal QCLOSELOCK_n (used for generating controlsignal EEPROG_ST), an end-of-loading signal QEOT of the thirteen databits (also used for generating control signal EEPROG_ST) and theaforementioned end-of-transmission signal EOTRANSMIT (used by generatorcircuit 80-FIG. 5-for initialising bistable trigger circuit S-Rdelivering signal TlMEOUT_n).

[0075] With reference to FIG. 10, an embodiment example of detectioncircuit 41 will now be presented. As illustrated, control signal OEemanating from control terminal PAD_OE is applied to the input of twoinverter circuits 415, 425, each including a p-MOS transistor 411, 421respectively, and an n-MOS transistor 412, 422 respectively, connectedgate to gate and drain to drain between supply potentials VDD andV_(SS). The first inverter 415 further includes a resistive element 410placed between the source of p-MOS 411 and potential VDD whereas thesecond inverter 425 includes a resistive element 420 placed between thesource of n-MOS 422 and potential V_(SS). Consequently, each inverterhas a response which could be termed asymmetrical and generates anoutput signal OE1, OE2 respectively, whose switching thresholdrespectively precedes or follows the passage of signal OE throughintermediate level V_(DD)/2 (or more exactly, (V_(DD)-V_(SS))/2). TheXOR logic combination allows a signal, designated DOE, to be delivered,passing to the high logic state in proximity to voltage level V_(DD)/2.

[0076] In this case, signals OE1 and OE2 are applied to the two inputsof an NXOR gate in order to deliver the inverse DOE_n of signal DOE.Signal DOE is applied to input D of a first bistable trigger circuit D431, its output signal QOEL being applied to input D of a secondbistable trigger circuit D 432 whose output delivers the aforementionedsignal QOE2. Each bistable trigger circuit is clocked by clock signal CKand initialised by initialisation signal RESET. The inverted outputsQOE1_n and QOE2_n of the two bistable trigger circuits 431 and 432, aswell as signal DOE_n are applied to the three inputs of an NOR gate inorder to generate communication mode activation signal PROG_EN.

[0077] Upon reading FIG. 10, it will easily be understood that signalPROG_EN remains at the high logic level as long as the three signalsDOE_n, QOE1_n and QOE2_n are at the low logic level. It will easily beunderstood that, following the return of signal PROG_EN to the low logiclevel (as soon as a substantially different voltage to V_(DD)/2 isapplied to control terminal PAD_OE), signal QOE2 is held at the highlogic level approximately during one period of clock signal CK, thusholding control signal PROG_ENHZ at the high logic level as alreadymentioned above.

[0078]FIG. 12 shows an embodiment example of output interface 49. Thisoutput interface essentially includes a multiplexer 490 (here with eightinputs) to the inputs of which are applied data bits EED[0] to EED[7]stored in EEPROM memory 30 and transmitted on data bus 48, a selectionstage 492 comprising two inputs onto which clock signals S4CK_n and S12CK_n are applied and a bistable trigger circuit D 494.

[0079] Selection signals S0, S1, S2 generated by control unit 48 assurethe sequential selection of data bits EED [0] to EEP [7] which aresuccessively transmitted by output terminal MUXOUT of multiplexer 490 tothe control input of selection stage 492. The output of this stage 492is applied to the clock input of bistable trigger circuit 494 via afirst NOR gate, the signal ENREAD_n being applied to the second input ofthis NOR gate. Input D of bistable trigger circuit 494 is at the highlogic level and its non-inverted output is applied to the input of asecond NOR gate at the second input of which is also applied the signalENREAD_n. This second NOR gate delivers at its output data signalDATA_OUT. Clocking signal S16CK and initialisation signal RESET areapplied to the inputs of a third NOR gate delivering an initialisationsignal RESDATAOUT_n to the inverted initialisation terminal of bistabletrigger circuit D 494. As illustrated in FIG. 6, signal S16CK has aleading edge coinciding with the sixteenth pulse of clock signal CK thusallowing periodic initialisation of bistable trigger circuit 494 at theend of the transmission of a bit.

[0080] Upon reading FIG. 12, it will easily be understood that, in readmode (ENREAD_n=0), as a function of the stored bit EED[i], clockingsignal S4CK_n (bit EED[i] to 0) or clocking signal S12CK_n (bit EED[i]to 1) is selected by stage 492 and the inverse of these signals isconsequently applied to the clock input of bistable trigger circuit D494. As illustrated in FIG. 6, signals S4CK_n and S12CK have a trailingedge (passage from the high logic level to the low logic level)coinciding with the fourth, respectively twelfth, pulse of clock signalCK.

[0081] Thus, if the stored data bit EED[i] has a value of 0, the outputof bistable trigger circuit 494 passes to the high logic state at theend of four pulses of signal CK and if data bit EED[i] has a value of 1,the output of the trigger passes to the high logic level at the end oftwelve pulses of clock signal CK. As the output Q of bistable triggercircuit 494 is inverted by the second NOR gate, it will be understoodthat signal DATA_OUT will actually have the shape shown in FIG. 6 as afunction of the bit to be transmitted.

[0082] Of course, if the read mode is not active (ENREAD_n=1), the clockinput of bistable trigger circuit D 494 as well as output DATA_OUT areblocked.

[0083] With reference to FIG. 11, a detailed embodiment example of readand write operation control unit 47 will now be described.

[0084] Control unit 47 includes first of all a first selection stage451, first and second bistable trigger circuits D460 and 461, a firstcounter 462 (here by eight) and a first logic circuit 465 connected tothe various stages of counter 462. These elements 451, 460, 461 and 462form, with the associated logic, a circuit generating clocking signalsSCK, S4CK_n, S12CK_n and S16CK.

[0085] Clock signal CKDATA_OUT (at 512 Hz in this example) and datasignal DATA originating from the input of shift register 43 are appliedto the first and second inputs of stage 451 whose output is applied tothe clock input of first bistable trigger circuit 460, the inverseRESET_n of the initialisation signal being applied to input D of thistrigger 460. The non-inverted output DATAQ of bistable trigger circuit460 is applied to the input of second bistable trigger circuit D 461 viaan XOR gate whose second input is coupled to the non inverted output ofsecond bistable trigger circuit 461. This non-inverted output of secondbistable trigger circuit 461 is also applied to the clock input ofcounter 462. The clock input of trigger D 461 is further clocked by thereverse CK_n of clock signal CK (2 kHz).

[0086] A memory element or latch 463 conventionally formed of twointerconnected NAND gates assures the production of an initialisationsignal EOB of counter 462 and of the two triggers D 460 and 461. Theinverse CK_n of clock signal CK is applied to a first input of latch 463(input terminal of the first NAND gate). The NAND logic combination ofsignal ENREAD_n and the output signal designated MAX of counter 462 (MAXpasses to the high logic level when the counter has reached its maximumcount), on the one hand, and the inverse RESET_n of the initialisationsignal, on the other hand, are applied to the other input of latch 463(input terminal of the second NAND gate). The initialisation signal EOBis picked up at the output of the second NAND gate.

[0087] Those skilled in the art will be perfectly able to understand theinteraction of the aforementioned elements upon reading FIGS. 6 and 11and the indications that have just been presented. It will simply benoted that selection stage 451 is controlled (by the OR logiccombination of signals TEN and ENREAD_n) to deliver signal DATA to theinput of bistable trigger circuit 460 when data is loaded in shiftregister 43 (TEN=1 or READEN_n=1) or to deliver clock signal CKDATA_OUTwhen read mode is activated (TEN=0 and READEN_n=0). Consequently,clocking signals SCK, S4CK_n, S12CK_n and S16CK are synchronised on theedges of data signal DATA when data is loaded in register 43 or on theedges of clock signal CKDATA_OUT when data is read.

[0088] Control unit 47 includes, secondly, a second selection stage 452,a second counter 455 (here by sixteen) and a second logic circuit 456connected to the stages of counter 455 to deliver selection signals DATAS0, DATA S1 and DATA S2. These elements 452, 455 and 456 form, with theassociated logic, a circuit generating activation signals CK4BITS, EOTand EOTREAD and selection signals S0, S1, S2 (formed respectively of theNOR logic combination of signal ENREAD_n and signals DATA S0, DATA S1,DATA S2). The signal CK4BITS is an end-of-transmission indicator of thefirst four data bits (i.e. the four key bits K[3] to K[0], and signalsEOT and EOTREAD are respectively indicators of the end of loading of thethirteen data bits (in write mode) and the end of generating outputsignal DATA_OUT (in read mode).

[0089] Clocking signal S16CK (a pulse at the end of transmission of abit) and clocking signal SCK (originating from the clocking signal ofshift register 43) are applied to the first and second inputs of stage452 whose output is applied to the clock input of counter 456 whoseinitialisation terminal is controlled by initialisation signal RESET.

[0090] Those skilled in the art will again be perfectly able tounderstand the interaction of the aforementioned elements upon readingFIGS. 6 and 11 and the indications that have just been given. It willsimply be noted that selection stage 452 is controlled (also by the ORlogic combination of signals TEN and ENREAD_n) so as to deliver signalSCK to the input of counter 455 when data is loaded in shift register 43(TEN=1 or READEN_n=1) or to deliver signal S16CK when read mode isactivated (TEN=and READEN_n=0).

[0091] Control unit 47 further includes a bistable trigger circuit D 471associated with a set of logic gates 470 to deliver, in particular, theaforementioned signals TEN, QEOT and OCLOSELOCK_n as well as two otherbistable trigger circuits D 472 and 473 associated with a second set oflogic gates 475 to deliver, in particular, signal ENREAD_n.

[0092] Write key activation signal CLOSELOCK_n delivered by unit 45 ofFIG. 9 is applied to input D of bistable trigger circuit 471. The latteris clocked by activation signal CK4BITS and includes an invertedactivation terminal (SET) connected to the inverse RESET_n of theinitialisation signal. The inverted output of bistable trigger circuit471 delivers signal QCLOSELOCK_n.

[0093] The set of logic gates 470 includes a first AND gate with twoinputs whose output is connected to a first NOR gate with two inputs,the other input of this NOR gate receiving signal EOT. The output ofthis NOR gate is applied, via an inverter (signal QEOT) to an inputterminal of the first AND gate, the other input of this AND gatereceiving the inverse RESET_n of the initialisation signal. The outputof the inverter (QEOT) is also connected to an input terminal of asecond NOR gate with three inputs whose output delivers signal TEN. Asecond input of this NOR gate with three inputs receives a signal QNREADoriginating from the inverted output of bistable trigger circuit D 472.The third input of the NOR gate originates from the output of a secondAND gate with two inputs connected respectively to the non invertedoutput QCLOSELOCK of bistable trigger circuit D 471 and the output oflogic circuit 456 delivering activation signal CK4BITS.

[0094] Read key activation signal READ_n delivered by unit 45 of FIG. 9is applied to input D of bistable trigger circuit 472. The latter isalso clocked by activation signal CK4BITS and includes an invertedactivation terminal (SET) connected to the inverse RESET_n of theinitialisation signal. The inverted output of bistable trigger circuit472 delivers signal QNREAD. The non inverted output QREAD of thisbistable trigger circuit 472 is connected to input D of bistable triggercircuit 473 clocked by a clock signal CKENREAD originating from the NORlogic combination of signal DATAQ originating from the aforementionedbistable trigger circuit D 460 and the inverse of clock signalCKDATA_OUT. It will have been understood that this clock signal CKENREADis inactive during data loading in shift register 43 (DATAQ=1) andcorresponds to signal CKDATA_OUT in the opposite case (DATAQ=0).

[0095] The set of logic gates 75 is substantially similar to set 470 andincludes a first AND gate with two inputs whose output is connected to afirst NOR gate with two inputs, the other input of this NOR gatereceiving signal EOTREAD. The output of this NOR gate is applied, via aninverter, (signal QEOTR) to an input terminal of the first AND gate, theother input of this AND gate receiving the inverse RESET_n of theinitialisation signal. The inverted output (QEOTR) is also connected toan input terminal of an NXOR gate with two inputs whose output deliverssignal ENREAD_n. The second input of this NXOR gate receives the signaloriginating from the inverted output of bistable trigger circuit D 473.

[0096] Finally, it will be noted that signal EOTRANSMIT transmitted togenerator circuit 80 of signals TIMEOUT_n and STARTUP (FIGS. 3 and 5) isproduced at the output of a NAND gate including two inputs respectivelyconnected to the inverses of signals QEOT and QEOTR of logic gate sets470 and 475.

[0097] Upon reading FIG. 11 and the indications hereinbefore, thoseskilled in the art will easily understand how the various elementspresented interact without it being necessary to dwell any longer onthis fact. It will simply be noted, according to the arrangementillustrated, that the non-inverted outputs of the two bistable triggercircuits D 471 and 472 are both at the high logic level while the systemis in initialisation mode (RESET=1) or while none of the write or readkeys has been loaded. In this state, the inverted output of bistabletrigger circuit D 473 is likewise at the low logic state.

[0098] During initialisation (RESET=1), the end-of-transmission signalsEOT (end of loading the thirteen data bits in write mode) and EOTREAD(end of generating output signal DATA_OUT in read mode) are at the lowlogic state. Signals QEOT and QEOTR delivered respectively by logic gatesets 470 and 475 are also at the low logic state. Taking account of thefact that activation signal CK4BITS and the inverted output QNREAD ofbistable trigger circuit D 472 are also both at the low logic level,signal TEN produced by logic gate set 470 is brought to the high logiclevel. Likewise, taking account of the fact that the inverted output ofbistable trigger circuit D 473 as well as signal QEOTR are both at thelow logic level, the output of the NXOR gate delivering signal READEN_nis also brought to the high logic level.

[0099] As soon as the initialisation signal is brought to the low logiclevel (RESET=0), signals QEOT and QEOTR are held at their initial lowlogic level, signals TEN and READEN_n keeping their high logic level.The two selection stages 451 and 452 are thus respectively controlled soas to select data signal DATA, on the one hand, and clocking signal SCKon the other hand.

[0100] As soon as the programming mode is activated (PROG_EN=1) and dataDATA are introduced in accordance with the aforementioned diagram,elements 460, 461, 462, 463 and 465 are activated to produce clockingsignals SCK, S4CK_n, S12CK_n and S16CK in synchronism with the leadingedge of each data bit introduced. The first data bits, in this case keybits K[3] to K[0], are thus transmitted and loaded in shift register 43(FIG. 9) and counter 455 counts the pulses of clocking signal SCKgenerated for loading bits in the shift register.

[0101] As soon as four pulses of signal SCK have been detected,activation signal CK4BITS passes to the high logic level, activatingbistable trigger circuit D 471 and 472. If the key bits K[3] to K[0] donot correspond to any of the defined read and write keys, bistabletrigger circuits D 471 and 472 keep their state, i.e. QCLOSELOCK andQREAD at the high logic level. In this situation, the passage to thehigh logic level of activation signal CK4BITS causes the closure of thesecond NOR logic gate (with three inputs) of set 470 and the passage ofcontrol signal TEN to the low logic level thus blocking any subsequenttransmission of data and any loading of data in shift register 43.

[0102] If the read key is correctly introduced (READ_n=0), this causesthe passage of signal QREAD to the low logic level and of its inverseQNREAD to the high logic level, and, as a result, the passage of controlsignal TEN to the low logic level. The subsequent introduction of datain the shift register is thus also interrupted (DATA=0).

[0103] As soon as the non inverted output signal DATAQ of bistabletrigger circuit D 460 again passes to the low logic level followinginitialisation of the latter via initialisation signal EOB, clock signalCKDATA_OUT is then applied to the clock input CKENREAD of bistabletrigger circuit D 473 causing the passage of its inverted output to thehigh logic level and, consequently, the passage of signal ENREAD_n tothe low logic level at the output of the NXOR gate of set 475.

[0104] The passage of signal ENREAD_n to the low logic level causes theswitching of the two selection stages 451 and 452 on the clock signalsCKDATA_OUT and S16CK respectively. The read process of the stored datais then undertaken in accordance with the diagram already described withreference to FIG. 12 until the moment at which the end of read signalEOTREAD passes to the high logic level at the end of the transmission ofthe eighth data bit EED[7]. This passage also causes the switching, inlogic gate set 475, of signal QEOTR to the high logic level and,consequently, the return of signal ENREAD_n to the high logic level atthe output of the NXOR gate.

[0105] In the event that the key introduced corresponds to the write key(CLOSELOCK_n=0), this causes the passage of signal QCLOSELOCK to the lowlogic level, ensuring that signal TEN is kept at the high logic level.The introduction of the remaining data bits (bits D[7] to D[0] andparity bit P) can thus continue. At the end of loading the thirteen databits, detected after counter 455 has counted the thirteen pulses ofsignal SCK, the end of data introduction signal EOT passes to the highlogic level, thus also causing, in logic gate set 470, the passage ofsignal QEOT to the high logic level and the passage of control signalTEN to the low logic level. The data entry is thus again interruptedupstream of shift register 43 (DATA=0).

[0106] With reference again to FIG. 9, if the parity of the data isverified (ENPARITY=1), the passage of signals QEOT and CLOSELOCK_n tothe high logic level combined with states QOE2=1, QOE1_n=1 (cf. above),TIMEOUT_n=1 and the pulses of clock signal CK, causes signal EEPROG_STto pass briefly (for the duration of a pulse of clock signal CK) to thehigh logic state, starting the write process of the data bits introducedD[7] to D[0] into the EEPROM memory.

[0107] Although the invention has been described within the scope of apreferred application, i.e. to adjusting a feature of an oscillatingcircuit, it will be noted that the programming principle that has justbeen described is also applicable to other electronic devices, such asintegrated sensors, having a feature that one would like to adjust. Itwill also be noted that although the feature adjusted in the exampledescribed is a capacitance value, the adjustment can be carried out onother elements of the oscillator circuit, such as the value of aresistive element or adjusting the division rate of a frequency dividercircuit. Nonetheless the oscillator circuit presented as an embodimentof the invention itself constitutes a very advantageous solution.

[0108] It will also be understood that various modifications and/orimprovements obvious to those skilled in the art can be made to theembodiment described in the present description without departing fromthe scope of the invention defined by the annexed claims. Thus, numerousalternative logical solutions are available to those skilled in the artto make the write and programming functions described. The inventionthus should not be limited to the strict configuration of the logiccircuits presented in the Figures.

1.-12. (canceled).
 13. An electronic device including an electroniccircuit for delivering an output signal and a programmable non volatilememory coupled to said electronic circuit to allow storage of a binaryword representative of at least one adjustable feature of saidelectronic circuit, this electronic device including at least first andsecond supply terminals to which first and second supply potentials areapplied, and at least one output terminal at which said output signalfrom the electronic circuit is delivered, wherein the electronic devicefurther includes: an output stage coupled to said electronic circuit andto said output terminal to set the latter in a first state, called thenormal state, in which said output signal from the electronic circuit isdelivered by said output terminal, or in a second state, called the highimpedance state, in which said output signal from the electronic circuitis not delivered by said output terminal and in which said outputterminal has a high output impedance; a control terminal and detectionmeans coupled to said output stage and to said control terminal todetect the application of a determined control signal at the controlterminal and, in response, to set said output terminal in said secondhigh impedance state a serial communication interface including at leastone data introduction terminal connected to said output terminal toreceive, in serial form, data bits transmitted via said output terminalwhen the latter is in said second high impedance state; and controlmeans connected to said serial communication interface and to saidnon-volatile memory for storing said transmitted data bits in saidnon-volatile memory.
 14. The device according to claim 13, wherein saidserial communication interface further includes a data extractionterminal for delivering, in serial form, data bits representative ofsaid binary word stored in said non volatile memory.
 15. The deviceaccording to claim 13, wherein said serial communication interfacefurther includes means for detecting a key transmitted via said outputterminal.
 16. The device according to claim 13, further including meansfor returning said output terminal to its first so-called normal stateat the end of a determined interval of time.
 17. The device according toclaim 13, wherein said electronic circuit is an oscillator circuitdelivering an oscillation signal at a determined frequency and whereinsaid adjustable feature of the device is a feature of said oscillatorcircuit.
 18. The device according to claim 17, wherein said oscillatorcircuit is an inverter type oscillator circuit including first andsecond load capacitors arranged at the input and output of saidoscillator circuit, and wherein the adjustable feature is thecapacitance value of at least one of said first and second loadcapacitors.
 19. The device according to claim 18, wherein at least oneof said load capacitors is formed of a network of a plurality ofcapacitors each able to be connected in parallel by means of a switchcontrolled by the state of a corresponding bit of said binary word. 20.The device according to claim 17, wherein said serial communicationinterface further includes a data extraction terminal for delivering, inserial form, data bits representative of said binary word stored in thenon volatile memory, and wherein said device further includes aselection stage connected to the output of said oscillator circuit andto said data extraction terminal of said serial communication interfaceto deliver either said oscillation signal or said data bitsrepresentative of said binary word stored in the non-volatile memory bysaid output terminal.
 21. The device according to claim 13, wherein saiddetection means are arranged to detect the application of a determinedcontrol signal substantially equal to half the supply voltage of theelectronic device.
 22. A method for programming and/or reading aprogrammable non volatile memory of an electronic device including anelectronic circuit for delivering an output signal, said programmablenon volatile memory being designed to allow storage of a binary wordrepresentative of at least one adjustable feature of said electroniccircuit, this electronic device including at least first and secondsupply terminals to which first and second supply potentials areapplied, and at least one output terminal at which said output signal ofthe electronic circuit is delivered, wherein this method includes thefollowing steps switching said output terminal into a so-called highimpedance state in which said output signal of the electronic circuit isnot delivered by said output terminal and in which this output terminalhas a high output impedance; introducing in serial form via said outputterminal data bits; and storing in said non volatile memory at least apart of said introduced data bits and/or reading at least a part of saidbinary word stored in said non volatile memory.
 23. The method accordingto claim 22, wherein the switching of said output terminal into saidhigh impedance state is carried out by applying a determined potentialto a control terminal of said electronic device.
 24. The methodaccording to claim 22, wherein said data bit introduction step includesthe prior introduction of a key and wherein said storage or read step isonly carried out if said key corresponds to a predetermined write key orread key.